1. Field
The various embodiments of the present invention relate to ultra-small pitch interconnect structures comprising of ultra-thin interposers having ultra-high density through vias defined therein.
2. Description of Related Art
The increasing number of smart and mobile phone applications, including video streaming, 3D graphics, camera-functions, and gaming, are driving the demand for logic to memory bandwidth (BW) at increasing levels without an increase in power consumption. Bandwidth is defined as bit rate per pin or I/O and the number of I/Os. Bit rate per pin is influenced by many factors, the most important factor being interconnection length between two devices. The main elements that influence bandwidth, therefore, are (1) the number of parallel interconnections between a logic and memory (IC) devices in a given area, referred to as I/O density, determined by the pitch of interconnections and (2) the length of such interconnections between the logic and memory devices.
FIG. 1 illustrates various 3D packaging schemes of the prior art and an illustration of an exemplary embodiment of the present invention (FIG. 1e). Briefly described, the packaging schemes are, for example, a system-in-package (SIP) structure (FIG. 1a), a package-on-package (POP) structure (FIG. 1b), a face-to-face (F2F) structure (FIG. 1c), and a logic on bottom stack (FIG. 1d) structure. The logic on bottom stack structure is a next generation configuration that utilizes 3D ICs with complex and expensive through silicon vias (TSVs).
The wire-bonded SIP and POP structures are limited in the number of chip-to-chip interconnections and the interconnection length, preventing these structures from providing high bandwidths without a significant increase in power consumption. The F2F structure achieves finer-pitch I/Os and thus increases the number of chip-to-chip interconnections, however, the design is limited to two chips and therefore cannot be scaled to multiple chips or sub-systems.
Silicon interposers with very high I/Os at finer pitches offer potential solutions to these problems of the prior art configurations, as multiple ICs may be placed side by side on the silicon interposer and connected through lateral re-distribution layer wiring. Such a structure has two limitations, however. First, this structure is very expensive to manufacture, attributed to the small number of interposers produced from 200-300 mm wafers as well as the expensive back-end-of-line (BEOL) processes. The second limitation is related to the electrical signal delay, due to both electrical lossiness of silicon as well the long wire lengths with high resistance.
An entirely new, complex, and expensive technology, called “3D ICs with TSVs”, is being developed worldwide in an effort to achieve ultra-high bandwidth using TSVs fabricated within logic, memory, and other ICs, and stacking these devices one on top of the other to enable ultra-fine pitch and ultra-short interconnections, as illustrated in FIG. 1d. However, this form of multi-die stacking with TSVs imposes great challenges in forming TSVs within complementary metal oxide semiconductor (CMOS) chips, power delivery, testability, reliability, and thermal management of logic chip, all of which remain major barriers in achieving high bandwidth for 3D ICs. Additionally, organic, ceramic, and glass carriers having conductive through vias have been described in prior art, however, they do not operate at high bandwidths because of coarse pitch and long interconnections. The interconnect structure of the present invention, a three-dimensional (3D) interposer, achieves the same ultra high density of interconnections at ultra short lengths, very similar to TSVs within the logic and memory devices. Such a structure serves many applications for heterogenous stacking of ICs that cannot be integrated into a single IC. One such application is for providing high bandwidth, comparing favorably over 3D ICs with TSVs, as it is scalable, testable, thermal manageable, and can be manufactured at lower costs.